MICRO PROCESSOR FOR CORTEX M3

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QUESTION 1:

                                What are the fundamentals of cortex M3 processor?

Fundamentals of Cortex M3

    The Cortex-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank,
and 32-bit memory interfaces. The processor has a Harvard architecture, which means it has a
separate instruction bus and data bus. the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces.

For complex applications that require more memory system features, the Cortex-M3 processor
has an optional MPU, and it is possible to use an external cache if it’s required. Both little
endian and big endian memory systems are supported.

A simplified View of Cortex M3

QUESTION 2:

                             Define registers and types of registers also explain their functions?

Registers

 The Cortex-M3 processor has registers R0 to R15. R13 (the stack pointer) is banked, with
only one copy of the R13 visible at a time.

R0 to R12: General-Purpose Registers

R0 to R12 are 32-bit general-purpose registers for data operations. Some 16-bit Thumb
instructions can only access a subset of these registers (low registers, R0 to R7).

R13: Stack Pointers

The Cortex-M3 contains two stack pointers, R13. They are banked so that only one is visible
at a time:

1.      Main Stack Pointer (MSP): The default stack pointer; used by the OS kernel and
exception handlers

2.      Process Stack Pointer (PSP): Used by user application code.

Registers In Cortex M3

The lowest two bits of the stack pointers are always 0, which means they are always word
aligned.
R14: The Link Register
When a subroutine is called, the return address is stored in the link register.
R15: The Program Counter
The program counter is the current program address. This register can be written to control the
program flow.
Special Registers

1.      The Cortex-M3 processor also has a number of special registers:

Program Status Registers (PSRs)

2.       Interrupt Mask Registers (PRIMASK, FAULTMASK, BASEPRI)

3.       Control Register (CONTROL)

Special Registers In Cortex M3

These registers have special functions and can be accessed only by special instructions. They
cannot be used for normal data processing.

Question 3:

                        Explain Operational Modes of Cortex M3 processor.

Operation Modes

The Cortex-M3 processor has two modes and two privilege levels.

1.      Thread Mode

2.      Handler Mode

Thread mode in which processor is executing normal codes it is either be a privileged level or unprivileged level.

Handler mode in which processor is executing an interrupt or system exception handler.

The privilege levels (privileged level and user level) provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model.

Operations Modes And Privilege Levels In Cortex M3

Allowed Operation Mode Transitions

Example with privileged accesses

           Usually used by the OS kernel, all memory location scan be accessed (unless prohibited by MPU setup). When the OS launches a user application, it is likely to be executed in the user access level to protect the system from failing due to a crash of untrusted user programs.

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